Welcome to CHDL

HOD Profile (ECE)

Faculty Name                                    Dr.V.Thrimurthulu
Date of Birth                         07-03-1971
Designation                           Professor & Head
Years of Experience             Teaching : 13 years    Industry :10 years
Email Id                                vtmurthy.v@gmail.com
Employment Status                Full Time – Ratified by JNTUA
Areas of Specalization         Antenna Designing, Microwave & Wireless communication
Qualification                         M.E., Ph.D.
Subjects Taught                   AWP, EMTL, EDC, MWE, CMC, PDC, RS, WCN
Papers Published                  40

Paper Publications:

  1. “Low Power Modeling Of Topologically Compressed Static FlipFlop” in International Journal Of Engineering And Computer Science ISSN:2319-7242 Volume 4 Issue 6 June 2015, Page No. 12293-12297.
  2. “VLSI MODELING OF SENSITIZATION INPUT VECTOR EFFECT ON PROPAGATION DELAY FOR 32 NM CMOS DESIGNS” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 05583; May 2015.
  3. “Optimized Design and Implementation of Ieee-754 Floating Point Processor” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 798-806.
  4. “VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 06596; June 2015.
  5. “VLSI HARDWARE MODELING OF DYNAMIC RNS STRUCTURE FOR HIGHEND COMPUTATIONS” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 06597; June 2015.
  6. “VLSI Modeling Side Channel attaches on Modern Cache Based Processors” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 1099-1102.
  7. “Hardware Modeling of sorting Mechanism for finding first Maxima/Minima Values for a set Greater than 2” Published in International Journal of Research(IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 662-668.
  8. “VLSI Modeling of Efficient Carry Select Adder with Redundant Encoding Technique” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version pages 657-662.
  9. “Computations Of Elementary Functions Based On Table Lookup And Interpolation” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622 ,Pages1-7.
  10. “VLSI Modeling Of High Speed Dedicated Short Range Communication Application Systems” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622 ,Pages36-40.
  11. DFE FOR CDMA SYSTEMS OVER FADING CHANNEL USING QPSK SIGNALING SCHEM” in the International Journal of Research in Electronics (IJRE), Volume 01, Issue 03 Year 2014, ISSN No:  2349-252X, Page no: 1-5.
  12. “Implementation of Multi Mode AES Algorithm Using Verilog” in International Journal of Engineering research (IJER) ISSN: 2319-6890(online), 2347-5013(print) Volume No.3, Issue No.12, pp: 780-785, 01 Dec. 2014.
  13. VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS” published in i-manager’s Journal on Electronics Engineering, Print ISSN: 2229-7286, E-ISSN: 2249-0760, Vol. 5 · No. 1 · September - November 2014, Pages 27-32.
  14. Efficient Sorting Mechanism for Finding First W Maximum/Minimum Values By Using B.W.A Architecture” published in i-manager’s Journal on Embedded Systems, Vol. 3  No. 3, August - October 2014  Pages 39-44.
  15. “Optimizing Data Encoding Schemes to Reducing Energy Consumption in Network on Chip” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622 ,Pages8-14.
  16. Static Power Reduction Using Reconfigurable Multi-Mode Switches” in IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 6, Ver. III (Nov - Dec. 2014), PP 25-31 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197.
  17. Power Risky Pattern Reduction by Launch on Capture and Weighted Switching Activity for At Speed Scan Based Testing” in the International Journal of Science and Engineering (IJSE) ISSN: 2347-2200, Volume-2 , Number-2, July-Dec-2014, Pages 81-90.
  18. "A New Compensation Technique for Stable The Gain of Sub-Micron Amplifiers" in the International Journal of Engineering research (IJER) ISSN: 2319-6890(online), 2347-5013(print) Volume No.3, Issue No.12, pp: 786-790 01 Dec. 2014.
  19. “Efficient Hardware Implementation for Advanced Encryption Standard With 256 Bit Key Lengths” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue, 18 August-2014, Pages: 3873-3877.
  20. Implementation Of Decimal Matrix Code For Correcting Cell Upsets In Static Random Access Memoriesin the International Journal of Electrical, Electronics and Data Communication (IJEEDC), ISSN: 2320-2084 Volume-2, Issue-10, Oct.2014, Pages 72-76.
  21. DESIGN OF REDUCED POWER FLIP FLOP BASED ON SIGNAL FEED THROUGH SCHEME” in the International Journal of Science and Engineering (IJSE) ISSN:2347-2200, Volume-2 , Number-2, July-Dec-2014, Pages 72-80.
  22. On Chip Generation Of Function Test For High Transition Faults Using Fixed Hardwarein the International Journal of Electrical, Electronics and Data Communication (IJEEDC), ISSN: 2320-2084 Volume-2, Issue-10, Oct.2014, Pages 77-81.
  23. Implementation of Multi-Bit flip-flop for Power Reduction in CMOS Technologies” in the International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) ISSN (Online): 2320-9801, ISSN (Print): 2320-9798, Vol.2, Special Issue 4, September 2014, Pages: 91-98.
  24. “Power Safe Test Pattern Refinement for Transition Fault Coverage for Speed Scan Based Testing” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue.20 September-2014, Pages: 4099-4105.
  25. Pipelined Routing Network for Multiprocessor System on Chip” in the International Journal of Advanced Computational Engineering and Networking (IJACEN), ISSN: 2320-2106. Volume-2 Issue-10, Oct-2014 PAGES 1-5.
  26. Implementation of Fixed Angle Rotation using Bi-Rotational CORDIC” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue.20 September-2014, Pages: 4056-4061.
  27. “AN INVESTIGATION ON DIFFERENT DATA TYPES PASSING THROUGH OFDM TECHNIQUE BY USING QPSK MODULATOR” in the INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN ENGINEERING, TECHNOLOGY AND SCIENCES (IJ-CA-ETS), ISSN: 0974-3596   | APRIL 2013- SEPT 2013 |   Volume 5 : Issue 2.
  28. A REVIEW OF ISSUES, APPLICATION AND OPPORTUNITIES IN INDOOR WIRELESS OPTICAL COMMUNICATION SYSTEMS” in "Role of Physics in Sustainable Development - RPSD2013” in the Indian Streams Research journal(ISRJ) ISSN:-2230-7850.
  29. Novel Practice Of Combating Design Challenges Using Special Cellsin  the  International Journal of Emerging Trends & Applications in Engineering Technology and Sciences (IJ-ETA-ETS) ISSN 0974-3588,Volume 5, Issue 1, JAN' 12 – JUNE' ’12, 2012.
  30. “Protocol Routing in Ad-hoc Sensor Networks” in the International Journal of Science and Technology (IJST) ISSN (Online):2250-141X, Volume 2 Issue 1, Feb.2012, Pages 13-21.
  31. “FIELD PROGRAMMABLE GATE ARRAY (FPGA) IMPLEMENTATION OF UNIVERSAL MODULATOR USING CO-ORDINATE ROTATION DIGITAL COMPUTER( CORDIC) ALGORITHM” in  the  International Journal of Computer Applications in Engineering Technology and Sciences(IJ-CA-ETS)  : ISSN 0974-3596   volume 4 Issue-1, Oct,2011-Mar 20112, Pages 129-135.
  32. “Reduction of Co Channel Interference in Cellular Systems” in the International Journal of Science and Technology (IJST) ISSN (Online):2250-141X, Volume 1 Issue 1,Nov.2011, Pages45-49.
  33. “Analysis of Non-Coherent Receiver for joint timing recovery and Data detection in DS-CDMA Systems“ in the International Journal of Computer Applications in Engineering Technology and Sciences (IJ-CA-ETS): ISSN 0974-3596   volume 4 Issue-2, April2012-September2012, Page 069-076.
  34. VLSI Modeling Of Side Channel Attacks On Modern Processors” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622 ,Pages20-25.
  35. “32nm Based High-Speed Low Calibrated Flash ADC comparator with improved ENOB” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622 ,Pages15-19.